Design Engineer @ National Institute of Electronics (NIE)

Job Specification: ------------------- - Work in digital design including RTL design experience - Work in setting up Power Distribution architecture, power intent specification and validation methodology - Proficiency with industry-standard EDA tools (e.g., Cadence, Synopsys, Mentor Graphics). - Defining methodology and creating infrastructure to support FPGA based prototyping - Flow automation scripts using Tcl, and shell scripts - Power user of industry standard RTL Design & Synthesis tools, along with sub-module and unit level testing. - Work on UVM and System Verilog. - Knowledge of best practices with respect to implementation of digital logic - Understanding of digital design flow including RTL simulation, logic synthesis, timing constraints, timing closure, back annotation of parasitics, gate level simulation, equivalence checking - Work in UART, SPI, I3C protocols and DSP algos. - Understanding of Design Verification and the ability to write self-checking test suites - Understanding of ASIC test methodology such as scan insertion, memory BIST and test pattern generation - Work with systems team to understand the top-level requirements of the digital functions and develop detailed specifications Qualification: --------------- - MS/M.Phil/BS/BE/ M.SC in Electronics/Electrical or relevant fields with minimum 03 years of experience in the field of microelectronics and chip design. Preference will be given to candidates having hands on experience on EDA tools. Domicile Quota: ------------------ - Sindh (R) – 01, KPK – 01 Location of Job: ------------------ - Islamabad - Age relaxation has already been added.