About this role
IP Design Director at Astera Labs. Location: Bengaluru, Karnataka, India. Role: designing RTL, integrating IP, ensuring timing Requirements: 12+ years digital design experience with RTL, System Verilog/Verilog, synthesis, timing closure, PCIe and processor IP (ARM/ARC); experience with pre-/post-silicon bring-up, UVM, Synopsys/Cadence tools, and scripting (Python/Perl). Category: Engineering Seniority: Senior Level Tools: Synopsys, Cadence, UVM, System Verilog, Verilog, Python, Perl, PCIe, ARM, ARC, RISC-V, CXL, NVLink, UALink, COSMOS, GDS Commitment: Full Time Workplace: Onsite Languages: English