About this role
Senior RTL Algorithm Engineer at Envisics. Location: Milton Keynes, Buckinghamshire, United Kingdom. Role: Taking ownership, Performing analysis, Transforming models Requirements: Senior RTL Algorithm Engineer with 6-8 years RTL design, Verilog/SystemVerilog, high-speed pipelined architectures, MATLAB/Python, FPGA/ASIC validation. Category: Engineering Seniority: Senior Level Tools: Verilog, SystemVerilog, MATLAB, Python, Modelsim, Questa Commitment: Full Time Workplace: Hybrid Languages: English