About this role
Senior Verification Engineer at Envisics. Location: Milton Keynes, Buckinghamshire, United Kingdom. Role: Generating Vplans, Constructing testbenches, Running simulations Requirements: Senior Verification Engineer with 7+ years in ASIC/IP verification, system verification, RTL/ASIC development, SystemVerilog, UVM, Verilog/VHDL, Tcl/Python. Category: Engineering Seniority: Senior Level Tools: SystemVerilog, UVM, Verilog, VHDL, Tcl, Python, Matlab, C/C++ Commitment: Full Time Workplace: Hybrid Languages: English