About this role
Senior PLL Design Engineer at Ethernovia, Inc.. Location: Utrecht, Delft?, Netherlands. Role: design PLLs, architect design, collaborate teams Requirements: MSc or PhD in Electrical Engineering; 8+ years of PLL design in advanced CMOS; RTL/Verilog/C++/Python; Ethernet AFEs experience a plus; fluent in English; located in Utrecht, Netherlands or willing to relocate. Category: Engineering Seniority: Senior Level Tools: RTL, Verilog, C++, Python, Ethernet AFEs, CMOS, Mixed-Signal IC design Commitment: Full Time Workplace: Onsite Languages: English