About this role
SoC RTL Design Engineer at TYLsemi, Inc.. Location: San Jose or Bangalore. Role: specifying architecture, coordinating interfaces, driving power Requirements: BS/MS in EE/Computer Engineering, 8+ years digital IC design with 3+ years owning chip infrastructure (clocking, power, reset or DFT). Strong SystemVerilog, experience with embedded microcontroller integration, reset-domain design, and power-intent (UPF/CPF). Category: Engineering Seniority: Senior Level Tools: SystemVerilog, UPF, CPF, PCIe, UCIe, UART, JTAG, RISC-V, ARM Cortex-M Commitment: Full Time Workplace: Onsite Languages: English