About this role
RTL Design Engineer at TYLsemi, Inc.. Location: Bangalore or India. Role: developing RTL, performing simulation, supporting integration Requirements: Bachelor's or master's in EE/Elec/Computer Engineering, 5+ years RTL design experience, proficiency with Verilog/SystemVerilog, CDC, low‑power design, synthesis/timing concepts, simulation/debugging, and scripting (Python/Perl/Shell/TCL). Category: Engineering Seniority: Senior Level Tools: Verilog, System Verilog, Python, Perl, Shell, TCL, UPF, CPF, AXI, AHB, APB, PCIe, DDR, Ethernet, CXL, UCIe, FPGA Commitment: Full Time Workplace: Hybrid Languages: English