About this role
Modeling Design Engineer at Lattice Overview. Location: Pune or Bayan Lepas. Role: developing models, validating models, mentoring engineers Requirements: Bachelor's or Master's in Electrical Engineering with 6+ years experience in circuit modeling and simulation; proficiency with SPICE, Verilog, VHDL, SystemVerilog, SystemC; strong analytical, communication, and leadership skills. Category: Engineering Seniority: Senior Level Tools: SPICE, Verilog, VHDL, SystemVerilog, SystemC Commitment: Full Time Workplace: Onsite Languages: English