About this role
Sr. Engineer, ASIC Design at Ayar Labs. Location: San Jose, California, United States. Role: Develop RTL, Verify blocks, Bringup debug Requirements: BS or MS in Electrical/Computer Engineering; 1+ years ASIC design; Verilog; ASIC verification tools; scripting; ability to work independently. Category: Engineering Seniority: Entry Level Tools: Verilog, Xcelium, VCS, Questa, Python, C, C++ Commitment: Full Time Workplace: Onsite Languages: English