About this role
Sr. Engineer, ASIC Design at Ayar Labs. Location: Bengaluru, Karnataka, India. Role: Develop RTL, Verify design, Bringup silicon Requirements: BS/MS in Electrical/Computer Engineering; 1+ years ASIC design; Verilog; ASIC verification tools; scripting/programming Category: Engineering Seniority: Senior Level Tools: Verilog, Python, C, C++, Xcelium, VCS, Questa, ASIC verification tools Commitment: Full Time Workplace: Onsite Languages: English