About this role
Junior IC Layout Design Engineer at IC Enable. Location: Richardson, Texas, United States. Role: supporting layout, performing verification, resolving issues Requirements: 1+ year IC layout and physical verification experience, U.S. person (ITAR) requirement, experience with Cadence Virtuoso/VXL and Assura (DRC/LVS/ERC), BS in Electrical Engineering, exposure to SKILL or Perl a plus. Category: Engineering Seniority: Entry Level Tools: Cadence Virtuoso, VXL, Assura, DRC, LVS, ERC, SKILL, Perl Certifications: itar Commitment: Full Time Workplace: Hybrid Languages: English