About this role
RTL Design/AMS Verification Engineer at IC Enable. Location: Richardson, Texas, United States. Role: developing rtl, verifying designs, running simulations Requirements: 5+ years IC design experience; Verilog RTL design and verification experience; Cadence/Synopsys flows; AMS simulation, synthesis and APR; Bachelor's degree in Electrical Engineering; US work authorization (ITAR) required. Category: Engineering Seniority: Senior Level Tools: Verilog, Cadence, Synopsys, Python, Perl, Tcl, SKILL Commitment: Full Time Workplace: Remote Languages: English