About this role
Integrated Circuit Design Verification Engineer at Snap Inc. Location: Vancouver or Washington or California or New York City. Role: verifying designs, developing testbenches, executing verification Requirements: 10+ years of ASIC design verification experience, BSEE or MSEE (or equivalent), strong UVM/SystemVerilog skills, Siemens Questa experience, scripting (TCL/Make/Perl/Python/Shell), and excellent communication. Category: Engineering Seniority: Senior Level Tools: UVM, SystemVerilog, Siemens Questa, TCL, Make, Perl, Python, Shell, Linux Commitment: Full Time Workplace: Onsite Languages: English