About this role
Integrated Circuit Design Verification Engineer at Snap Inc. Location: Vancouver, Washington, United States. Role: designing display, developing testbenches, creating automation Requirements: 10+ years ASIC design verification experience; strong UVM/SystemVerilog skills; Siemens Questa; develop UVM/assertion testbenches, functional and code coverage, scripting/automation in Linux. Category: Engineering Seniority: Senior Level Tools: UVM, SystemVerilog, Siemens Questa, TCL, Make, Perl, Python, Shell, Linux Commitment: Full Time Workplace: Onsite Languages: English