About this role
ASIC Design Verification Engineer at AMD. Location: Markham or Ottawa. Role: planning verification, building tests, debugging failures Requirements: Plan, build, and execute IP-level ASIC verification for wired networking; develop UVM/SystemVerilog testbenches, debug RTL, use simulation tools, and script in Perl/Python/Makefile/shell. Bachelors required in CE/EE/CS. Category: Engineering Seniority: Mid Level Tools: UVM, SystemVerilog, Perl, Python, Makefile, Shell, Linux, Microsoft Windows Commitment: Full Time Workplace: Hybrid Languages: English