About this role
In this role you will help develop FPGA designs for Viasat next generation terminal products, including interfaces and high speed signal processing algorithms and/or network protocols in FPGAs. The individual will be responsible for the full design phase starting from the requirements' phase to documentation, block diagrams, implementation of source code, simulation, place & route, testing in hardware, and integration. The day to day: Collaborate with team members to jointly develop high-speed digital signal processing and waveform processing algorithms supporting satellite communications applications Develop testbenches and help maintain and update system level verification environment Synthesize Verilog and System Verilog for Altera and Xilinx/AMD FPGAs Develop timing constraints, analyze timing results, and implement design changes required to close timing Generate and collaborate on required design documents, development requirements, specifications and verification protocols Responsible for owning and driving technical issues to resolution Integrate and debugs design in the laboratory What you'll need: Bachelor's Degree in Electrical Engineering, Computer Engineering or a related field 10-12 years FPGA design experience, including Altera Quartus and Xilinx Vivado Strong knowledge of System Verilog Experience with RTL design for various signal processing blocks, including but not limited to equalizers, correlators, filters, FEC encoders and decoders Proven track record to design and implement FPGA modules using System Verilog with simulation and testbench development Work independently, take initiative, and take ownership of tasks and results Strong written and verbal communication skills, ability to work with a geographically distributed team