Senior ASIC Verification Engineer, System Verilog @ Paventia AB

Long experience from ASIC verification and test bench development Good knowledge of System Verilog and VHDL Experience from working with simulation tools such as Mentor and Cadence Experience from block level and sub-system level test benches using UVM Experience with version control systems English (verbal and writing) The project scope is to develop new radio technology for 5G and some new radio based products for 4G. You will work with functional verification of new ASICs and FPGAs. The work will be carried out in close cooperation with RTL designers. The work includes: Verification planning Verification specification Verification environment (creation/adaptation/maintenance). Test case creation Usage of uVC´s Development of uVC´s (if needed) Usage of reference models (if needed) Constrained random testing Creation of Coverage matrix Writing Verification Reports You will work as a consultant at our customers' sites paventia.se