About this role
ASIC Verification Engineer required with at least 10 years’ experience in ASIC Functional Verification. Required skills: Very good knowledge of Verilog, System Verilog and UVM methodology. Long experience in creating/adapting/maintaining block level and system level test benches using UVM/OVM. Long experience in creating verification plans, test cases for constrained random testing, coverage matrix, verification reports, usage/creation of UVC’s, usage of reference models Experience with simulation tools from vendors like Mentor, Cadence, and Synopsis. Experience in ARM CPU subsystems verification. Experience is C programming. Must be fluent in English. Additional skills: Knowledge and experience in debugging Ethernet, Wi-Fi, Bluetooth domain protocols. Unix/Linux, shell, Perl scripting experience.