About this role
Salary: £? - ? per year
Requirements
- Strong hands-on experience in digital design verification using SystemVerilog and UVM
- Experience modifying, extending, and debugging existing UVM testbenches and reusable verification components
- Good understanding of constrained-random verification, functional coverage, assertions, scoreboards, and checkers
- Experience in subsystem-level or SoC-level functional verification
- Strong understanding of SoC architectures, bus protocols, register interfaces, and processor-controlled peripherals
- Experience developing, executing, or debugging embedded C tests for processor-based SoC verification
- Strong debugging and analytical skills, including the ability to debug complex RTL simulation failures using industry-standard simulators and waveform debugging tools
- Experience executing regressions, analyzing failures, and driving functional coverage closure
- Working knowledge of scripting languages such as Python, Perl, or shell scripting
- Familiarity with version control systems and verification development workflows
- Understanding of ARM processor-based SoC architecture
- Ability to adapt existing verification environments to evolving design requirements
Responsibilities
- Perform subsystem-level and SoC-level functional verification using SystemVerilog and UVM
- Perform processor-driven verification using C-based test programs executing on embedded processor cores
Technologies
- ARM
- Embedded
- Perl
- Python
- SystemVerilog
- Hardware
- Verilog
More
We are seeking experienced SoC Design Verification Engineers to work on verification of a next-generation, multi-die System-on-Chip (SoC) design.
last updated 46 week of 2026