About this role
Salary: £86,324 - 103,589 per year
Requirements
- Strong, senior-level design verification experience
- Hands-on experience with UVM and SystemVerilog
- Mixed-signal verification experience
- A proactive, hands-on approach and willingness to take ownership
- Nice to have: Analog/mixed-signal modelling experience, such as real-number modelling or Verilog-AMS
- Nice to have: Experience guiding or leading verification work on a team
Responsibilities
- Own verification of mixed-signal ICs, from test planning through final sign-off
- Build and maintain UVM testbenches, coverage models, and regression suites
- Work closely with analog and digital design teams to identify issues early in the design cycle
- Track coverage and drive closure against the verification plan
- Help shape the teams verification approach and support other engineers
Technologies
- Support
- SystemVerilog
- Verilog
- Hardware
More
We are a global semiconductor manufacturer seeking a Senior Staff Verification Engineer to join our mixed-signal IC team in Cork and play a key role in bringing new products to market. This is a permanent, hybrid role based in Cork. Reperio Human Capital acts as an Employment Agency and an Employment Business.
last updated 44 week of 2026