About this role
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
- Work with R&D to identify and scope opportunities for the Cadence functional logic verification platform
- Understand the Goal and Objective, then plan and execute and manage key technical evaluations by co-working proactively with existing and potential customers as well as team colleagues
- Summarize the tasks and projects, and report to manager and share with team effectively
- Train, ramp-up and accompany customer project.
- Conduct basic and advanced trainings, presentations and demos as necessary.
- Ramp-up other members of the team on the advanced verification technologies and tools.
- Providing technical expertise to address clients’ queries, which need expert involvement
- The candidate should possess minimum BS level of CS or EE with 3-5 years of industry experience.
- Minimum 3 years hands-on, high expertise on hardware design & verification techniques.
- Hands on experience using HDL simulator (e.g. ies, vcs or questa, but ies preferred) is a must.
- Experience of RTL design or verification with Verilog / SV Language or C/C++ or System C.
- Understanding standard BUS protocol like AMBA or interface protocol.
- Hands on Verification experience using SystemVerilog/Verilog/VHDL/SystemC.
- Experience on UVM methodology or similar one should be preferred.
- Hands on Design experience using SystemVerilog, Verilog and VHDL.
- Knowledge of VIPs, and code & functional coverage tools (IMC preferred) and technologies.
- Knowledge of Metric Driven Verification (MDV) using vManager CS should be preferred.
- Hands-on experience optimizing RTL, Gate-level simulation for improving performance by using standard profiling tools is a big plus.
- Good communication skills in English and a strong desire for working in a global environment with customers and BU people.
We’re doing work that matters. Help us solve what others can’t.