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Design Verification Engineer @ Microtech Global Ltd

GBOnsiteFull-time
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About this role

Salary: £50,000 - 90,000 per year

Requirements

  • BEng, BSc, MEng, MSc, or equivalent qualification in Electronics, Computer Science, or a related discipline
  • Proven track record delivering first-time success with complex mixed-signal ICs
  • Experience with metric-driven verification, including planning, requirements extraction, directed and constrained-random verification, and functional and code coverage analysis
  • Knowledge of SystemVerilog, including SystemVerilog Assertions (SVA)
  • Testbench design experience using verification frameworks such as UVM, OVM, e, or VMM
  • Strong RTL and testbench debugging skills, including gate-level SDF
  • Strong problem-solving, analytical, and interpretation skills, with an innovative and creative approach
  • Preferred: experience with formal verification and verification qualification techniques
  • Preferred: scripting experience with Ruby, sh/csh, TCL, Make, or Perl
  • Preferred: power-aware verification using CPF/UPF
  • Preferred: object-oriented programming and OOP design patterns
  • Must be within commuting distance of an office or willing to relocate before employment

Responsibilities

  • Define IC verification plans that link product requirements to detailed test cases
  • Lead verification engineers in delivering thoroughly verified ICs
  • Create reliable, reusable testbenches for complex subsystems and ICs
  • Participate in verification specialist groups and contribute to methodology improvements
  • Support and coach the verification team in following and enhancing defined methodology practices
  • Take hands-on part in project design and verification activities

Technologies

  • Hardware
  • Support
  • OOP
  • Perl
  • Ruby
  • SystemVerilog

More

We are seeking Design Verification Engineers at all levels to join our Hardware & Software – Hardware department in Newbury or Edinburgh, England. The role focuses on digital verification for complex mixed-signal IC development and contributing to advanced projects and verification methodologies. This is a full-time hybrid position, with two days per week in the office; office days are based on business needs and team preference.

last updated 43 week of 2026

Skills

System VerilogSystemVerilog AssertionsUVMOVMVMMgate-level SDFconstrained random verificationcode coverage analysisformal verificationRubysh/cshTCL

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