About this role
Envision Employment Solutions is currently looking for a DFT Architect (Physical Design & Chiplet) for one of our partners, an IT Services and IT Consulting company.
THE ROLE
Testing a single die is hard enough. Testing a system of chiplets means rethinking test access, coverage and diagnosis from the ground up. You'll define the DFT architecture for complex, multi die designs and make sure it works hand in hand with physical design.
WHAT YOU'LL DO
Define DFT architecture and strategy for SoC and chiplet based designsOwn test access across dies, including JTAG, IJTAG and IEEE 1500/1838 approachesSet ATPG and scan compression strategy to meet coverage and test cost targetsWork closely with physical design on DFT timing, placement and routing impactDrive test coverage analysis and improvement across the chipLead DFT methodology, reviews and mentoring for the DFT teamSupport silicon bring up and diagnosis
WHAT WE'RE LOOKING FOR
10+ years of DFT experience, including architecture level ownershipDeep knowledge of ATPG, scan compression, JTAG, MBIST and LBISTExperience with chiplet or multi die test strategies is a strong plusSolid understanding of physical design and how DFT affects itExperience with Tessent, Synopsys or Cadence DFT toolsScripting in Tcl, Perl or PythonStrong technical leadership skills
YOU'LL THRIVE HERE IF YOU
You think about test from the first architecture meeting, not the lastYou enjoy solving problems that don't have a textbook answer yetYou work as comfortably with PD engineers as with test engineersYou measure your success in coverage and in silicon resultsYou want to lead DFT strategy for the next generation of designs