About this role
Internal
Digital Design Engineer
Responsibilities
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Architect, design, and verify complex digital front-end circuits and systems for FPGA and ASIC implementations, including defining digital design requirements, developing architectural specifications, and coding high-quality HDL modules that meet performance, reliability, and scalability targets.
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Execute all assigned tasks with strong focus on reusability, efficiency, and area-optimized design.
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Lead/participate in comprehensive design reviews, providing clear, constructive feedback to enhance design robustness, quality, and development efficiency.
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Apply mixed-signal understanding (is a strong plus) to ensure smooth integration of digital front-end architectures with analog and mixed-signal components.
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Proactively define optimal system and component-level concepts, driving digitization initiatives in close collaboration with engineers from all relevant disciplines.
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Collaborate with cross-functional engineering teams (eg. application and system engineers) to establish cost-effective solutions that meet functional, performance, and architectural objectives.
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Provide technical guidance and mentorship during reviews and technical discussions, contributing to a culture of engineering excellence.
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Continuously refine and enhance digital design methodologies, development workflows, and toolchains to increase productivity and design consistency.
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Create and maintain comprehensive digital design documentation, including requirements, architecture descriptions, design specifications, and block-level details.
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Document and/or review design processes, verification strategies, test plans, and results in compliance with industry standards and best practices.
Required Qualifications
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Master’s or PhD in Electronics Engineering or a related technical field with 6+ years of relevant experience, or a Bachelor’s degree with 8+ years of experience in digital design, SoC integration, or ASIC digital architecture.
Internal
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Strong proficiency in hardware description languages (HDLs) such as Verilog and SystemVerilog or VHDL.
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Proven track record of delivering complex digital design projects and collaborating effectively across multidisciplinary teams.
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Deep expertise in ASIC and FPGA design methodologies, including front-end architecture and implementation flows.
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Working knowledge of UVM is a strong plus.
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Experience with Design for Testability (DFT) and Design for Manufacturing (DFM) practices, is a plus.
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Strong understanding of the digital design flow, including synthesis, simulation, static timing analysis, and related front-end development processes.
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Hands-on experience with formal verification tools, such as Siemens Questa Formal and Synopsys Spyglass.
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Good understanding of CDC (Clock Domain Crossing), RDC (Reset Domain Crossing), and multi-power-domain design techniques.
B.E/ BTech in E&C (Masters in VLSI recommended)
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