About this role
Detailed task description
Experience: 6 - 12 Years
Collect, discuss, and evaluate requirements related to IC test & validation concept(s) in cooperation with other disciplines' developersActively support system and/or IC concept and architecture definition, considering feasibility with semiconductor technologies and test strategyApply new validation concepts to the design verification.Define requirements of the IC validation together in cooperation with other disciplines' developersSpecify IC validation characteristics and interfaces within component specification documentResponsible for the technical communication with the ASIC supplier during the whole ASIC developmentJudge and approve simulation/design results in consideration of defined system requirementsDecide on optimal IC verification concept based on simulation results and worst-case calculationsEvaluate technical and development risks for IC development together with ASIC PMPlan time schedule for dedicated ASIC project tasks, track validation progress, perform bench testsCreate and maintain development documentsApply configuration and change management, apply quality assurance managementFrom circuits specifications, ASIC verification engineer should specify verification strategies and testbench architectures (SystemVerilog, UVM, C-driven, others) to ensure optimum verification coveragesElaborate detailed verification plans corresponding to circuit specificationsDevelop verification environments and tests/sequences according to verification plansResponsible of the definition of the verification strategies, of their implementation and of the verification qualityImprove the verification flowHe is responsible for carrying out all assigned tasks with a focus on function, quality, test architecture, test coverage, schedule, and delivery of verification in time.Together with other disciplines' developers, the verification engineer is defining integration concepts, specifying the IC test requirements, defining related test architecture, and verifying implemented functions. The is taking care about process implementation and scheduleIC (ASIC) Verification The engineer is responsible for developing functional models for Analog and/or Digital IPs. Developing Digital and analog/mixed-signal test benches, Interaction between IPs at chip level (analog and digital), developing test benches, Functional verification, Technical support of co-workers and IP designers, Provide technical support to test engineers Master of Science in Electrical Engineering/Microelectronics/ VLSI design or similar qualification.Bachelor of science with advanced course in VLSI Design. REQUIRED KNOWLEDGE
* Organizational Standard Process and Methods (Risk Management, Project Management..)
* Knowledge of test tools, automation
* System Requirements
* System Architecture
* Functional Safety Management (ISO26262)
* System Security & Privacy Engineering (UNECE WP29)
* Communication
* Knowledge of test process, test methods, techniques and tools
* Capability to analyse and solve problems
* Product knowledge (for his responsiblity
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