About this role
About Us
Epia Neuro is a neural technology company developing intent-driven systems designed to restore function and independence for people living with neurological conditions. Its platform integrates implantable neural interfaces, adaptive algorithms, and assistive devices to translate neural intent into real-world action. The company's initial focus is stroke-related motor impairment, with expansion into cognitive decline and other neurological disorders, focusing on long-term solutions for the growing aging population.
The Role
We're looking for a Principal Design Engineer, Analog Mixed-Signal (AMS) to own the custom analog/mixed-signal ASIC at the heart of our implantable system. You'll own the chip architecture end to end: turning system requirements and early design work into the blueprint the team builds from - a complete design specification and implementation plan, revised wherever the requirements or silicon reality demand it. You'll personally design the most critical analog blocks at transistor level, direct the rest, and carry the chip through tapeout and silicon bring-up. On a small team, you'll make the calls a larger company would split across several people, and you'll own the results.
What You'll Do
Own the chip-level architecture: turn system requirements and our existing architecture concept into a written, reviewable design specification and implementation plan
Document your work continuously, including design choices, tradeoffs, and verification results, and treat documentation as a first-class deliverable
Personally design the most critical low-noise, ultra-low-power analog and mixed-signal blocks for an implantable device (e.g., neural recording front-ends, ADCs, bandgap references, clocks, power management), and direct the design of the rest across the team and partners
Run the full verification loop: pre- and post-layout simulation, corners and Monte Carlo, and SOA/reliability/aging checks appropriate for a long-life implant
Build behavioral models (Verilog-A/AMS, SystemVerilog) to support top-level and mixed-signal verification
Drive process/foundry, IP, and vendor decisions (foundry, layout, OSAT/packaging, test services)
Lead design reviews, mentor engineers, and set documentation and design-reproducibility standards for the team
Work closely with layout, digital, system, and test engineers, and own post-silicon bring-up and debug in our lab
Qualifications
10+ years of hands-on experience owning AMS IC designs, with multiple tapeouts carried through to silicon validation
Lead the architecture or analog specification of at least one chip from concept to silicon
Deep transistor-level expertise in low-noise and/or ultra-low-power precision analog
Strong reliability-first design approach: ESD, device breakdown/SOA, aging, and yield
Fluency in the Cadence Virtuoso/Spectre flow and a Linux-based, scripted, version-controlled design environment
BS, MS, or PhD in Electrical Engineering or a related field (MS or PhD preferred)
Nice to Have
ASIC design for biomedical, implantable, or neural-interface applications
High-voltage or specialty process experience (e.g., BCD, SOI)
Experience working directly with foundries and OSATs, including process selection and packaging decisions
Familiarity with medical-device development under design controls (e.g., ISO 13485 / FDA QMSR) or active-implant standards (e.g., ISO 14708)
Experience with open-source IC tools or flows
Prior experience at an early-stage company or as a first/senior analog hire
How We Work
We are intentional. We prioritize and are thoughtful about how we use others' time.
We care for others. We prioritize safety both for patients and one another.
We own outcomes, not just tasks. Our work demands the highest standards because it impacts real patients and real lives.
Humility is a strength. We are honest about what we know and what we don't know. Getting it right matters more than being right.
Location
This role is based in Alameda, CA, on site 4 days a week - hands-on lab access and bring-up are part of the job.
Benefits
Competitive base salary with equity
100% of healthcare coverage for you and your dependents
Generous vacation policy
Paid parental leave
Work from our waterfront office in Alameda, CA, with access to collaborative spaces and labs