About this role
Responsibilities:
• Implement and verify Scan, MBIST, and Boundary Scan solutions for complex SoC designs. • Perform scan insertion, DFT DRC checking, and scan chain validation to ensure testability and design quality. • Analyze fault coverage and develop ATPG patterns for production silicon testing. • Develop and maintain DFT automation flows and scripts using Tcl, Perl, Python, or Shell • Collaborate with SoC Design, Verification, Physical Design, and Test Engineering teams to resolve DFT and test-related issues throughout the product development cycle. • Support silicon bring-up, diagnosis, and yield improvement activities during product ramp-up and production. Requirements:
• Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Computer Science, or a related field. • 1-3 years of experience in VLSI design, DFT, or a related semiconductor engineering field. • Strong communication and interpersonal skills, with the ability to work effectively in a global team environment. • Good command of English; CET-6 or equivalent English proficiency is preferred. • Good knowledge of Design-for-Test (DFT) methodologies, including Scan, MBIST, and Boundary Scan. • Proficiency in Verilog, VHDL, and scripting languages (such as Tcl, Perl, Python, or Shell). • Hands-on experience with SoC DFT design and implementation for large-scale chips is a plus. • Familiarity with ASIC/SoC development flow, verification, and implementation processes is preferred.
More information about NXP in Greater China...
#LI-6650