About this role
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Position Overview
Join a growing and dynamic IP team developing best-in-class digital and mixed-signal IP solutions. This role focuses on post-sales technical support for high-performance interface IP, working as part of a team supporting UCIe, PCIe, USB, DPHY, Ethernet, DDR, LPDDR, GDDR, and HBM PHYs.
The Principal Product Engineer is a key technical leader and product owner, responsible for driving product engineering activities across the full lifecycle-from pre-sales engagement and pre-silicon integration to post-silicon bring-up and customer deployment. This role serves as a primary interface between customers and Cadence R&D, leading technical discussions, resolving complex issues, and ensuring successful product adoption.
This position requires strong technical depth, customer-facing leadership, excellent communication skills, and the ability to drive execution across global, cross-functional teams.
Key Responsibilities
Act as the primary product engineering owner for memory subsystems (DDR, LPDDR, GDDR, HBM, etc) at the customer levelLead customer engagements, drive technical discussions, design reviews, and deployment strategyOwn and drive resolution of complex subsystem integration and implementation issuesLead SoC integration reviews covering PHY and controller subsystemsProvide technical leadership for RTL, gate-level simulations, and timing closure strategiesDefine and drive improvements to integration methodologies, checklists, and customer collateralLead post-silicon bring-up and debug activities, ensuring successful customer deploymentCollaborate cross-functionally with R&D, validation, and applications teams to deliver product readinessDrive continuous improvement in customer experience, turnaround time, and engineering qualityMentor junior engineers and provide technical guidance across projects and teamsLeverage AI tools to improve debug efficiency, data analysis, and decision-making Position Requirements
Strong experience with high-speed interface IPDeep understanding of RTL design, gate-level verification, and simulation methodologiesExperience with synthesis, STA, and timing closure; backend knowledge is a plusFamiliarity with DFT methodologies, test flows, and system validation approaches Skills & Qualifications
[Required]
Bachelor's in electrical engineering, Computer Engineering, or related field with 7+ years of experience, or Master's with 5+ years, or PhD with relevant experienceProven ability to solve complex technical problems and drive root cause to closureExperience leading cross-functional technical efforts across design, validation, and customer teamsStrong communication skills with ability to influence customer and internal stakeholdersExperience managing multiple priorities, escalations, and technical reviewsDemonstrated ability to represent the organization in customer-facing technical rolesStrong ownership mindset and ability to drive deliverables independently [Preferred]
Experience with memory and/or high-speed communication interfaces (DDR, LPDDR, PCIe, Ethernet, UCIe, USB)Understanding of analog/mixed-signal design practicesExperience in customer-facing silicon debug and bring-up environmentsFamiliarity with AI-assisted workflows and data-driven debug techniques We're doing work that matters. Help us solve what others can't.