About this role
onsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world.
More details about our company benefits can be found here:
https://www.onsemi.com/careers/career-benefits
About the Role
onsemi is seeking a DFT Engineer to support the design and implementation of Design‑for‑Test (DFT) features for complex ASIC/SoC products across automotive and industrial applications. This role focuses on scan, ATPG, MBIST, and boundary scan, with close collaboration across design, PD, and test teams.
Key Responsibilities
• Develop and integrate DFT architectures including Scan, ATPG, MBIST, and JTAG • Implement and debug DFT logic to ensure high fault coverage and test quality • Generate and analyze ATPG patterns using industry‑standard tools • Support at‑speed and transition fault testing • Collaborate with RTL, Physical Design, STA, and Test Engineering teams • Address timing, CDC, and low‑power DFT considerations • Support test coverage analysis, DFT signoff, and silicon bring‑up
• #LI-RT1
Required Qualifications
• 3–5 years of experience in ASIC / SoC DFT • Strong understanding of: • Scan, ATPG, MBIST, JTAG • Fault models: stuck‑at, transition, at‑speed
• Hands‑on experience with DFT tools such as: • Synopsys DFT Compiler / TestKompress • Siemens Tessent or equivalent
• Familiarity with timing, CDC, and low‑power DFT flows • BS/MS (B.Tech/M.Tech) in Electrical Engineering or related field #LI-RT1
Preferred Qualifications
• Experience with advanced nodes and large SoCs • Exposure to physical‑aware DFT and test‑related ECOs • Working knowledge of UPF and low‑power test strategies • #LI-RT1