About this role
Responsibilities:
• Lead subsystem and SoC-level RTL integration for complex SoC products from architecture definition through tape-out. • Own and maintain SOC RTL integration, including IP assembly, connectivity, configuration, and design quality checks. • Define and implement SoC interconnect, clocking, reset, and power architectures to meet performance, power, and functional requirements. • Collaborate closely with architects to translate architectural specifications into robust RTL implementations. • Work with IP, Verification, DFT and Physical Design teams to resolve integration challenges and drive project milestones. • Drive continuous improvement of SoC integration methodologies, automation flows, and design quality.
Requirements:
• 5+ years (Senior level) of ASIC/SoC design and integration experience.
• Strong Verilog coding skills with solid understanding of digital logic design
• Deep understanding of AMBA (AXI/AHB/APB) protocols and NoC/NIC based architectures
• Strong knowledge of low power design methodologies
• Experience with industry-standard EDA tools for lint, CDC, RDC, and low-power verification
• Knowledge of automotive/industrial functional safety is a strong plus.
• Excellent communication and cross-functional collaboration skills.
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