We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, <a href="http://www.teradyne.com/">Teradyne</a> companies deliver manufacturing automation across industries and applications around the world! We attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive. Our Purpose TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supported to innovate and learn something new every day. We cultivate a culture of inclusion for all employees that respects their individual strengths, views, and experiences. We believe that our differences enable us to be a better team – one that makes better decisions, drives innovation and delivers better business results. Opportunity Overview Digital functional verification engineers responsible for the planning, strategy, and execution of challenging FPGA verification projects. Work under the technical supervision of a Verification Lead. The position requires interfacing with other functional groups (e.g. Hardware, software, applications). All About You We seek individuals who share our passion and determination. Our commitment to customer success drives us to go the extra mile. If you’re ready to join us in this mission, take a closer look at the minimum criteria for the position. <ul style="margin-bottom:0.0in;margin-top:0.0px"> <li style="line-height:18.0pt;margin:0.0in 0.0in 0.0in 0.0px;font-size:12.0pt;font-family:arial, helvetica, sans-serif">Master’s Degree or equivalent in Electrical Engineering/Computer Engineering/Computer Science or closely related field with a minimum of 6 years of relevant work experience OR Bachelor’s Degree or equivalent in Electrical Engineering/Computer Engineering/Computer Science or closely related field with a minimum of 8 years of relevant work experience </li> <li style="line-height:18.0pt;margin:0.0in 0.0in 0.0in 0.0px;font-size:12.0pt;font-family:arial, helvetica, sans-serif">Experience with Verification Test Plan (e.g. Cadence ePlanner) </li> <li style="line-height:18.0pt;margin:0.0in 0.0in 0.0in 0.0px;font-size:12.0pt;font-family:arial, helvetica, sans-serif">Experience with EDA Tools (e.g. Cadence Xcelium, Simvision)</li> <li style="line-height:18.0pt;margin:0.0in 0.0in 0.0in 0.0px;font-size:12.0pt;font-family:arial, helvetica, sans-serif">Experience with System Verilog Constraint Random Testing, Assertions and Functional Coverage </li> <li style="line-height:18.0pt;margin:0.0in 0.0in 0.0in 0.0px;font-size:12.0pt;font-family:arial, helvetica, sans-serif">Experience with UVM Testbench Components development and integration</li> <li style="line-height:18.0pt;margin:0.0in 0.0in 0.0in 0.0px;font-size:12.0pt;font-family:arial, helvetica, sans-serif">Experience with UVM Tests sequences development and testing</li> <li style="line-height:18.0pt;margin:0.0in 0.0in 0.0in 0.0px;font-size:12.0pt;font-family:arial, helvetica, sans-serif">Expertise with Verification IP integration</li> <li style="line-height:18.0pt;margin:0.0in 0.0in 0.0in 0.0px;font-size:12.0pt;font-family:arial, helvetica, sans-serif">Experience with System Verilog/UVM based reference models/Predictors development and integration </li> <li style="line-height:18.0pt;margin:0.0in 0.0in 0.0in 0.0px;font-size:12.0pt;font-family:arial, helvetica, sans-serif">Experience with Industry Standard Protocols (e.g. AXI, PCIe, DDR3/4/5) </li> <li style="line-height:18.0pt;margin:0.0in 0.0in 0.0in 0.0px;font-size:12.0pt;font-family:arial, helvetica, sans-serif">Experience working with revision source control (e.g. clearcase, git, svn)</li> <li style="line-height:18.0pt;margin:0.0in 0.0in 10.0pt 0.0px;font-size:12.0pt;font-family:arial, helvetica, sans-serif">Detailed oriented with the ability to bring issues to closure. </li> </ul> Desired (but not required) skills/experience: <ul style="margin-bottom:0.0in;margin-top:0.0px"> <li style="line-height:18.0pt;margin:0.0in 0.0in 0.0in 0.0px;font-size:12.0pt;font-family:arial, helvetica, sans-serif">Experience in FPGA design implementation with System Verilog</li> <li style="line-height:18.0pt;margin:0.0in 0.0in 0.0in 0.0px;font-size:12.0pt;font-family:arial, helvetica, sans-serif">Experience in verification of Automated Test Equipment functionality </li> <li style="line-height:18.0pt;margin:0.0in 0.0in 10.0pt 0.0px;font-size:12.0pt;font-family:arial, helvetica, sans-serif">Experience writing automation scripts (e.g. Make files, shell programming, TCL, Perl, Python)</li> </ul> Compensation: The base salary range for this role is $135,400 - $216,600. This range is a good faith estimate, and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location. Incentive Plan: This job is eligible for discretionary bonus(es) based on financial performance. Benefits:Teradyne offers a variety of robust health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more. Please click <a style="color:inherit" href="https://www.teradyne.com/2026-benefit-information-for-us-employees/" target="_blank" rel="noopener">here</a> to see details #LI-KC2

Digital Verification Engineer (MTD, San Jose, CA) (San Jose, CA, US) @ Teradyne Inc

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