About this role
Job Description
Job Title: Principal Hardware ASIC Architect Engineer
Hyderabad, India
About the Role
We are seeking an experienced Hardware Architect with strong expertise in SOC-architecture, Micro-architecture design, RTL coding and system-level performance/power analysis. The ideal candidate will have a track record of owning complex blocks or subsystems from concept through silicon, balancing performance, power, and area (PPA), and working closely with software, asic-design, asic-verification, asic-physicaldesign teams. it requires deep architectural insight and hands-on implementation understanding to help guide design trade-offs and drive the next generation of AI inference accelerators. This is what you are responsible for Architecture & Micro-Architecture
• Define product feature and capabilities and own the architecture for compute, memory, interconnect & high-speed interface subsystems in the AI inference chip. • Collaborate with various software teams to co-optimize hardware features for AI workloads. • Collaborate with RTL designers to identify complex technical issues/risks. Review and guide RTL implementation, ensuring consistency with architectural intent and timing/power goals • Collaborate with Physical-design teams for Area/Floorplan refinement, Timing targets etc. • Define and document interface specifications, control/status logic, and pipeline structures.
• Lead PPA analysis and trade-off discussions across RTL and architecture. AI Workloads & HW-SW Co-Design
• Collaborate closely with various software to co-optimize hardware features for real-world AI inference workloads. • Incorporate considerations such as, quantization, sparsity, dataflow, scheduling, memory bandwidth into architectural decisions. • Guide hardware features that improve programmability, debuggability, and long-term software scalability. Modelling & Analysis
• Develop and maintain high-level architecture and performance models. • Use simulation and architectural models to guide RTL-level improvements. • Validate model predictions against RTL or emulation results and refine accordingly. • Strong understanding of AI inference workloads, dataflows, quantization, and memory/bandwidth bottlenecks in edge deployments Necessary Qualifications:
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field. • 12+ years of experience in SOC design, SOC architecture, RTL design, micro-architecture.
• Strong understanding of computer architecture, memory hierarchies, SoC interconnects, and AI/ML compute architectures. • Proven experience optimizing for performance, power, and area. • Hands-on expertise in Verilog/SystemVerilog, C/C++, and scripting (Python/Tcl/Perl) Preferred Qualifications:
• Experience with AI accelerators, DSPs, or high-performance CPUs/GPUs. • Familiarity with performance modeling frameworks (e.g., Python/C++ based). • Exposure to EDA tools, power/performance analysis, and hardware-software co-design. • Strong analytical skills and a collaborative mindset.
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