About this role
<p style="text-align:left"><span style="font-size:10.0pt"><span style="font-family:Arial, Helvetica, sans-serif">We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, <a href="http://www.teradyne.com/">Teradyne</a> companies deliver manufacturing automation across industries and applications around the world!</span></span></p> <p style="text-align:left"> </p> <p style="text-align:left"><span style="font-size:10.0pt"><span style="font-family:Arial, Helvetica, sans-serif">We attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive.</span></span></p><div> <div> <p><strong><span style="font-family:arial, helvetica, sans-serif"><span>Our Purpose </span> </span></strong><br><span style="font-family:arial, helvetica, sans-serif"><span>TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supported to innovate and learn something new every day.</span> </span><br><span style="font-family:arial, helvetica, sans-serif"> </span><br><span style="font-family:arial, helvetica, sans-serif"><span>We cultivate a culture of inclusion for all employees that respects their individual strengths, views, and experiences. We believe that our differences enable us to be a better team – one that makes better decisions, drives innovation and delivers better business results.</span><span> </span></span></p> </div> <div> <p><span style="font-family:arial, helvetica, sans-serif"> </span></p> </div> <div> <p><strong><span style="font-family:arial, helvetica, sans-serif"><span>Opportunity Overview</span><span> </span></span></strong></p> </div> <div> <p><span style="font-family:arial, helvetica, sans-serif"><span>Teradyne’s Memory Test Division (MTD) seeks a motivated and technically driven FPGA Engineer to support the development of our growing portfolio of cutting-edge memory test solutions.</span><span> </span></span></p> </div> <div> <p><span style="font-family:arial, helvetica, sans-serif"> </span></p> </div> <div> <p><span style="font-family:arial, helvetica, sans-serif"><span>MTD creates advanced solutions for complex testing applications, driving innovation through creativity and diverse perspectives. Our test instrumentation supports the world’s most advanced memory technologies, combining state-of-the-art digital and analog designs, cutting-edge ASIC/FPGA technologies, liquid cooling, and high-performance signal delivery.</span><span> </span></span></p> </div> <div> <p><span style="font-family:arial, helvetica, sans-serif"> </span></p> </div> <div> <p><span style="font-family:arial, helvetica, sans-serif"><span>We are looking for an FPGA Design Engineer with exceptional technical skills and a strong desire to collaborate on team-oriented projects. Success in this role means delivering high-quality, reliable products to market quickly. If you are excited to join a dynamic, global team, Teradyne may be the place for you!</span><span> </span></span></p> <p> </p> </div> <div> <ul style="list-style-type:disc"> <li style="font-family:arial, helvetica, sans-serif"> <p><span style="font-family:arial, helvetica, sans-serif"><span>Architect and implement FPGA solutions to support next generation Flash and DRAM test instrumentation.</span><span> </span></span></p> </li> </ul> </div> <div> <ul style="list-style-type:disc"> <li style="font-family:arial, helvetica, sans-serif"> <p><span style="font-family:arial, helvetica, sans-serif"><span>Provide technical guidance to junior engineers</span><span> </span></span></p> </li> </ul> </div> <div> <ul style="list-style-type:disc"> <li style="font-family:arial, helvetica, sans-serif"> <p><span style="font-family:arial, helvetica, sans-serif"><span>Turn abstract concepts and customer requirements into reliable, extensible, and supportable designs. </span><span> </span></span></p> </li> </ul> </div> <div> <ul style="list-style-type:disc"> <li style="font-family:arial, helvetica, sans-serif"> <p><span style="font-family:arial, helvetica, sans-serif"><span>Assist in the maintenance and extension of existing FPGA designs to support quality improvement and emerging customer requirements.</span><span> </span></span></p> </li> </ul> </div> <div> <ul style="list-style-type:disc"> <li style="font-family:arial, helvetica, sans-serif"> <p><span style="font-family:arial, helvetica, sans-serif"><span>Maintain schedule commitments and deliver high quality end products.</span><span> </span></span></p> </li> </ul> </div> <div> <ul style="list-style-type:disc"> <li style="font-family:arial, helvetica, sans-serif"> <p><span style="font-family:arial, helvetica, sans-serif"><span>Occasional travel may be required.</span><span> </span></span></p> </li> </ul> </div> <div> <p> </p> <p><strong><span style="font-family:arial, helvetica, sans-serif"><span>All About You</span> </span></strong><br><span style="font-family:arial, helvetica, sans-serif"><span>We seek individuals who share our passion. Our commitment to customer success drives us to go the extra mile. If you’re ready to join us in this mission, take a closer look at the minimum criteria for the position.</span><span> </span></span></p> <p> </p> </div> <div> <ul style="list-style-type:disc"> <li><span style="font-family:arial, helvetica, sans-serif"><span>Bachelor’s Degree or equivalent in Electrical Engineering or a closely related field with a minimum of 5 years of relevant work experience, or Master’s Degree or equivalent with a minimum of 3 years of relevant work experience.</span></span></li> <li style="font-family:arial, helvetica, sans-serif"> <p><span style="font-family:arial, helvetica, sans-serif"><span>Experience with Digital Design and Architecture</span><span> </span></span></p> </li> </ul> </div> <div> <ul style="list-style-type:disc"> <li style="font-family:arial, helvetica, sans-serif"> <p><span style="font-family:arial, helvetica, sans-serif"><span>RTL coding, synthesis, timing closure and lab validation</span><span> </span></span></p> </li> </ul> </div> </div> <div> <div> <ul style="list-style-type:disc"> <li style="font-family:arial, helvetica, sans-serif"> <p><span style="font-family:arial, helvetica, sans-serif"><span>Experience with Static Timing Analysis of ASICs or FPGAs</span><span> </span></span></p> </li> </ul> </div> <div> <ul style="list-style-type:disc"> <li style="font-family:arial, helvetica, sans-serif"> <p><span style="font-family:arial, helvetica, sans-serif"><span>Experience with digital simulation testbench creation</span><span> </span></span></p> </li> </ul> </div> <div> <ul style="list-style-type:disc"> <li style="font-family:arial, helvetica, sans-serif"> <p><span style="font-family:arial, helvetica, sans-serif"><span>Experience with C or C++</span><span> </span></span></p> </li> </ul> </div> <div> <ul style="list-style-type:disc"> <li style="font-family:arial, helvetica, sans-serif"> <p><span style="font-family:arial, helvetica, sans-serif"><span>Familiarity with lab equipment such as oscilloscopes, power supplies and waveform generators. </span></span></p> </li> </ul> <p style="font-family:arial, helvetica, sans-serif"> </p> <p style="font-family:arial, helvetica, sans-serif"><strong><span style="font-family:arial, helvetica, sans-serif"><span>Additional Desired Skills</span></span></strong></p> <p style="font-family:arial, helvetica, sans-serif"> </p> </div> <div> <ul style="list-style-type:disc"> <li style="font-family:arial, helvetica, sans-serif"> <p><span style="font-family:arial, helvetica, sans-serif"><span>FPGA Transceiver based design experience</span><span> </span></span></p> </li> </ul> </div> <div> <ul style="list-style-type:disc"> <li style="font-family:arial, helvetica, sans-serif"> <p><span style="font-family:arial, helvetica, sans-serif"><span>Experience with DRAM and Flash Memory interfaces</span><span> </span></span></p> </li> </ul> </div> <div> <ul style="list-style-type:disc"> <li style="font-family:arial, helvetica, sans-serif"> <p><span style="font-family:arial, helvetica, sans-serif"><span>Experience with Altera/AMD FPGA tool flows</span><span> </span></span></p> </li> </ul> </div> <div> <ul style="list-style-type:disc"> <li style="font-family:arial, helvetica, sans-serif"> <p><span style="font-family:arial, helvetica, sans-serif"><span>Proficiency with Verilog HDL Language</span><span> </span></span></p> </li> </ul> </div> <div> <ul style="list-style-type:disc"> <li style="font-family:arial, helvetica, sans-serif"> <p><span style="font-family:arial, helvetica, sans-serif"><span>Familiarity with UVM Methodology</span><span> </span></span></p> </li> </ul> </div> <div> <ul style="list-style-type:disc"> <li style="font-family:arial, helvetica, sans-serif"> <p><span style="font-family:arial, helvetica, sans-serif"><span>Scripting languages experience </span><span> </span></span></p> </li> </ul> </div> <div> <ul style="list-style-type:disc"> <li style="font-family:arial, helvetica, sans-serif"> <p><span style="font-family:arial, helvetica, sans-serif"><span>Linux and Windows operating systems experience</span><span> </span></span></p> </li> </ul> </div> <div> <ul style="list-style-type:disc"> <li style="font-family:arial, helvetica, sans-serif"> <p><span style="font-family:arial, helvetica, sans-serif"><span>Familiarity with ATE instrumentation</span><span> </span></span></p> </li> </ul> </div> <div> <p> </p> <p><strong><span style="font-family:arial, helvetica, sans-serif"><span>Compensation:</span> </span></strong><br><span style="font-family:arial, helvetica, sans-serif"><span>The base salary range for this role is $135,400 - $216,600. This range is a good faith estimate, and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location. </span><span> </span></span></p> </div> <div> <p><span style="font-family:arial, helvetica, sans-serif"><span> </span><span> </span></span></p> </div> <div> <p><span style="font-family:arial, helvetica, sans-serif"><span><strong>Incentive Plan:</strong> </span><span>This job is eligible for discretionary bonus(es) based on financial performance. </span><span> </span></span></p> </div> <div> <p><span style="font-family:arial, helvetica, sans-serif"><span> </span><span> </span></span></p> </div> <div> <p><strong><span style="font-family:arial, helvetica, sans-serif"><span>Benefits:</span><span> </span></span></strong></p> </div> <div> <p><span style="font-family:arial, helvetica, sans-serif"><span>Teradyne offers a variety of robust health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more. Please click </span><a href="https://www.teradyne.com/2026-benefit-information-for-us-employees/" target="_blank" rel="noreferrer noopener"><span>here</span></a><span> to see details. </span><span> </span></span></p> </div> <div> <p><span style="font-family:arial, helvetica, sans-serif"> </span></p> </div> <div> <p><span style="font-family:arial, helvetica, sans-serif"><span>#LI-KC2</span> </span><br><span style="font-family:arial, helvetica, sans-serif"> </span><br><span style="font-family:arial, helvetica, sans-serif"> </span></p> </div> </div>