We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, <a href="http://www.teradyne.com/">Teradyne</a> companies deliver manufacturing automation across industries and applications around the world! We attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive. Our Purpose TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought within our workforce. Our employees are supported to innovate and learn something new every day. We cultivate a culture of inclusion for all employees that respects their individual strengths, views, and experiences. We believe that our differences enable us to be a better team – one that makes better decisions, drives innovation and delivers better business results. Opportunity Overview Teradyne’s Memory Test Division (MTD) seeks a motivated and technically driven FPGA Manager to support the development of our growing portfolio of cutting-edge memory test solutions. MTD creates advanced solutions for complex testing applications, driving innovation through creativity and diverse perspectives. Our test instrumentation supports the world’s most advanced memory technologies, combining state-of-the-art digital and analog designs, cutting-edge ASIC/FPGA technologies, liquid cooling, and high-performance signal delivery. We are looking for a hands-on FPGA Engineering Manager to oversee the development of cutting-edge memory test solutions. This role combines technical oversight, project management and direct engineering contributions, ensuring the successful delivery of high-quality, reliable products that support the world’s most advanced memory technologies. Your key responsibilities as FPGA Engineering Manager will be: <ul style="margin-bottom:0.0in;margin-top:0.0px" type="disc"> <li style="color:black;line-height:115%;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:10.0pt;font-family:Calibri, sans-serif">Plan, prioritize, and manage multiple FPGA development projects, ensuring on-time delivery within budget and scope.</li> <li style="color:black;line-height:115%;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:10.0pt;font-family:Calibri, sans-serif">Represent the FPGA team on project core teams and at program reviews.</li> <li style="color:black;line-height:115%;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:10.0pt;font-family:Calibri, sans-serif">Provide support for sustaining issues.</li> <li style="color:black;line-height:115%;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:10.0pt;font-family:Calibri, sans-serif">Work closely with cross-functional teams, including hardware, software, and firmware engineers, to ensure seamless integration of FPGA designs into larger systems.</li> <li style="color:black;line-height:115%;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:10.0pt;font-family:Calibri, sans-serif">Recruit, onboard, and retain top engineering talent to build a high-performing team.</li> <li style="color:black;line-height:115%;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:10.0pt;font-family:Calibri, sans-serif">Set goals and conduct regular performance conversations for a team of 4 to 6 engineers.</li> <li style="color:black;line-height:115%;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:10.0pt;font-family:Calibri, sans-serif">Contribute to FPGA team process improvement initiatives.</li> <li style="color:black;line-height:115%;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:10.0pt;font-family:Calibri, sans-serif">Provide hands-on technical guidance to the FPGA engineering team, including reviewing and contributing to FPGA architectures, designs, and specifications.</li> <li style="color:black;line-height:115%;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:10.0pt;font-family:Calibri, sans-serif">Actively participate in FPGA design and development, including RTL coding, synthesis, timing closure, and lab validation.</li> </ul> All About You We seek individuals who share our passion. Our commitment to customer success drives us to go the extra mile. If you’re ready to join us in this mission, take a closer look at the minimum criteria for the position. <ul style="margin-bottom:0.0in;margin-top:0.0px" type="disc"> <li style="color:black;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:10.0pt;font-family:Calibri, sans-serif">B.S. or M.S. in Electrical Engineering or closely related discipline </li> <li style="color:black;line-height:115%;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:10.0pt;font-family:Calibri, sans-serif">12+ years of relevant experience in Digital ASIC or FPGA design</li> <li style="color:black;line-height:115%;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:10.0pt;font-family:Calibri, sans-serif">Minimum of 5 years of experience as an FPGA/ASIC project lead, driving multiple projects through concept development, architectural exploration, design implementation, lab validation, and production release. </li> <li style="color:black;line-height:115%;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:10.0pt;font-family:Calibri, sans-serif">Extensive experience coding RTL (verilog preferred). </li> <li style="color:black;line-height:115%;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:10.0pt;font-family:Calibri, sans-serif">Extensive experience using digital simulation tools (Cadence preferred). </li> <li style="color:black;line-height:115%;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:10.0pt;font-family:Calibri, sans-serif">Extensive experience using static timing analysis tools. </li> <li style="color:black;line-height:115%;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:10.0pt;font-family:Calibri, sans-serif">Experience designing with the following: PCIe, DDR3/4/5, AXI, ethernet, SPI, SERDES </li> <li style="color:black;line-height:115%;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:10.0pt;font-family:Calibri, sans-serif">Experience with either AMD or Altera FPGAs and development tools (Vivado/Quartus), preferably both. </li> <li style="color:black;line-height:115%;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:10.0pt;font-family:Calibri, sans-serif">Experience using digital design quality tools e.g. Lint, CDC. </li> <li style="color:black;line-height:115%;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:10.0pt;font-family:Calibri, sans-serif">Experience with bug tracking tools</li> <li style="color:black;line-height:115%;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:10.0pt;font-family:Calibri, sans-serif">Experience with source control systems and continuous integration. </li> <li style="color:black;line-height:115%;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:10.0pt;font-family:Calibri, sans-serif">Familiarity with digital verification tools and methodologies (preferably UVM). </li> <li style="color:black;line-height:115%;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:10.0pt;font-family:Calibri, sans-serif">Experience with project scheduling tools</li> <li style="color:black;line-height:115%;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:10.0pt;font-family:Calibri, sans-serif">Excellent presentation and communication skills. </li> </ul> Additional Desired Skills: <ul style="margin-bottom:0.0in;margin-top:0.0px" type="disc"> <li style="color:black;line-height:115%;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:10.0pt;font-family:Calibri, sans-serif">Experience developing hardware for automated test equipment </li> <li style="color:black;line-height:115%;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:10.0pt;font-family:Calibri, sans-serif">Experience as a first level manager of an engineering team. </li> <li style="color:black;line-height:115%;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:10.0pt;font-family:Calibri, sans-serif">Experience with FPGA Transceiver based designs</li> <li style="color:black;line-height:115%;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:10.0pt;font-family:Calibri, sans-serif">Experience with DRAM and Flash Memory interfaces</li> <li style="color:black;line-height:115%;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:10.0pt;font-family:Calibri, sans-serif">Experience with Linux and Windows operating systems</li> <li style="color:black;line-height:115%;margin-top:0.0in;margin-right:0.0in;margin-bottom:0.0in;font-size:10.0pt;font-family:Calibri, sans-serif">Familiarity with ATE instrumentation</li> </ul> Compensation: The base salary range for this role is $171,000-$273,600. This range is a good faith estimate, and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location. Incentive Plan: This job is eligible for discretionary bonus(es) based on financial performance. Benefits: Teradyne offers a variety of robust health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more. Please click <a href="https://www.teradyne.com/2026-benefit-information-for-us-employees/" target="_blank" rel="noopener">here</a> to see details. #LI-KC2

FPGA Engineering Manager (MTD, San Jose, CA) (San Jose, CA, US) @ Teradyne Inc

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