About this role
Digital Design Engineer for High-end Communication-IP-Cores (all genders) at Fraunhofer-Gesellschaft. Location: Dresden, Saxony, Germany. Role: developing cores, implementing designs, supporting customers Requirements: Completed bachelor’s degree in electrical engineering/microelectronics/computer science, ≥2 years professional experience, strong VHDL/Verilog/SystemVerilog skills, FPGA/ASIC toolchain experience (Vivado, Cadence), German and English (B2). Category: Engineering Seniority: Entry Level Tools: VHDL, Verilog, SystemVerilog, Vivado, Cadence, HLS, SystemC, virtual prototyping Commitment: Full Time, Part Time Workplace: Hybrid Languages: German, English