About this role
Digital Design Engineer für High End Kommunkations-IP-Cores (all genders) at Fraunhofer-Gesellschaft. Location: Dresden, Saxony, Germany. Role: developing IP-cores, implementing designs, supporting customers Requirements: Bachelor in electrical engineering/microelectronics/computer science, ≥2 years experience, strong VHDL/Verilog/SystemVerilog skills, FPGA/ASIC toolchain knowledge (Vivado, Cadence), timing constraints, German and English (B2). Category: Engineering Seniority: Entry Level Tools: VHDL, Verilog, SystemVerilog, Vivado, Cadence, HLS, SystemC, Virtual Prototyping, RISC-V Commitment: Full Time Workplace: Onsite Languages: German, English