About Us STARK is a new kind of defence technology company revolutionizing the way autonomous systems are deployed across multiple domains. We design, develop and manufacture high performance unmanned systems that are software-defined, mass-scalable, and cost effective. This provides our operators with a decisive edge in highly contested environments.We’re focused on delivering deployable, high-performance systems - not future promises. In a time of rising threats, STARK is bolstering the technological edge of NATO Allies and their Partners to deter aggression and defend Europe - today. Your mission As a Junior FPGA Engineer, you will join our specialized hardware team to develop the high-speed digital logic that powers our autonomous platforms. You will be responsible for designing, implementing, and testing FPGA-based solutions that process complex signals in real-time.This role is ideal for a high-potential engineer who wants to move beyond simulation and see their code interact with the physical world. You will work closely with senior mentors to bridge the gap between digital signal processing theory and hardware realisation. Responsibilities We are looking for candidates with experience in some or all of the following areas:<ul style="margin-top:0;margin-bottom:0;"><li style="list-style-type:disc;font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;">RTL Design: Develop and maintain high-speed digital logic using VHDL, Verilog, or SystemVerilog.</li><li style="list-style-type:disc;font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;">Verification: Create testbenches and run functional simulations to validate design behavior.</li><li style="list-style-type:disc;font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;">Hardware Debugging: Use lab equipment (Oscilloscopes, Logic Analyzers) and on-chip debugging tools (ILA/Signal Tap) to troubleshoot physical hardware.</li><li style="list-style-type:disc;font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;">Integration: Collaborate with Electronics and Software teams to define FPGA pinouts, review schematics, and develop interface APIs.</li><li style="list-style-type:disc;font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;">IP Management: Integrate and configure third-party IP cores and interface with high-speed ADCs/DACs.</li><li style="list-style-type:disc;font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;">Documentation: Maintain clear design specifications, register maps, and version-controlled HDL repositories.</li></ul> Qualifications <ul style="margin-top:0;margin-bottom:0;"><li style="list-style-type:disc;font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;">Proficiency in VHDL, Verilog, or SystemVerilog.</li><li style="list-style-type:disc;font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;">Experience with FPGA vendor tools (e.g., Xilinx Vivado or Intel Quartus).</li><li style="list-style-type:disc;font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;">Understanding of Digital Signal Processing (DSP) fundamentals.</li><li style="list-style-type:disc;font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;">Basic experience with simulation tools (e.g., ModelSim, Questa).</li><li style="list-style-type:disc;font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;">Familiarity with common hardware interfaces (AXI, SPI, I2C, UART).</li><li style="list-style-type:disc;font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;">Competency in Python or C/C++ for scripting and testing support.</li></ul><h2 style="line-height:1.38;margin-top:18pt;margin-bottom:4pt;">Soft Skills</h2><ul style="margin-top:0;margin-bottom:0;"><li style="list-style-type:disc;font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;">Curiosity-Driven: You have a deep desire to understand how things work at the register level.</li><li style="list-style-type:disc;font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;">Resilient: You enjoy the "puzzle" of hardware debugging and timing closure.</li><li style="list-style-type:disc;font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;">Effective Communicator: You can explain your logic design clearly to both software and hardware teams.</li></ul><h2 style="line-height:1.38;margin-top:18pt;margin-bottom:4pt;">Qualifications</h2><ul style="margin-top:0;margin-bottom:0;"><li style="list-style-type:disc;font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;">Bachelor’s or Master’s degree in Electrical, Electronic, or Computer Engineering.</li><li style="list-style-type:disc;font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;">0-2 years of experience (relevant internships or personal hardware projects are highly valued).</li></ul><h2 style="line-height:1.38;margin-top:18pt;margin-bottom:4pt;">Nice to Have</h2><ul style="margin-top:0;margin-bottom:0;"><li style="list-style-type:disc;font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;">Knowledge of System-on-Chip (SoC) architectures (e.g., Zynq).</li><li style="list-style-type:disc;font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;">Familiarity with Linux-based development environments.</li><li style="list-style-type:disc;font-size:11pt;font-family:Arial, sans-serif;color:#000000;background-color:transparent;font-weight:400;font-style:normal;text-decoration:none;">Interest in software-defined radio (SDR) architectures.</li></ul>

Junior FPGA Engineer (All Genders) @ Stark

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