About this role
Sr. Engineer, ASIC Design Verification at Ayar Labs. Location: Bengaluru, Karnataka, India. Role: Develop testbenches, Analyze coverage, Implement DFT Requirements: 2+ years ASIC verification; SystemVerilog/UVM; scripting; experience with mixed-signal/AMS modeling; testbench development; DFT knowledge. Category: Research and Development (R&D) Seniority: Senior Level Tools: SystemVerilog, UVM, NCSIM, VCS, ModelSim, Python, AMS, WREAL, SerDes, HBM Commitment: Full Time Workplace: Onsite Languages: English