About this role
CENTRALE LYON - Doctorant Conception de circuit ferroélectrique pour la logique ternaire at CENTRALE LYON. Location: Ecully, Auvergne-Rhône-Alpes, France. Role: designing circuits, modeling devices, characterizing circuits Requirements: Master's degree required; strong background in digital circuit design, semiconductor/device physics, Verilog-A/VHDL/Verilog and Python; experience with Cadence/Spectre and Synopsys preferred; scientific English required. Category: Research and Development (R&D) Seniority: Entry Level Tools: Cadence Virtuoso, Spectre, Synopsys, Verilog-A, VHDL, Verilog, Python Commitment: Full Time, Contract Workplace: Onsite Languages: English, French