About this role
RISC-V CPU Architect/RTL Lead at JDWK Inc.. Location: Austin, Texas, United States. Role: Own RTL implementation, Evaluate open-source cores, Architect enhancements Requirements: 7+ years RTL design; CPU/microarchitecture; RISC-V ISA; open-source cores; SystemVerilog/Verilog; EDA tools; verification; startup environment. Category: Engineering Seniority: Senior Level Tools: SystemVerilog, Verilog, UVM, EDA tools, open-source RISC-V cores Commitment: Full Time Workplace: Remote Languages: English