About this role
Principal ASIC Architect at Tensordyne. Location: Sunnyvale, California, United States. Role: Leading architecture, Defining specifications, Mentoring teams Requirements: Lead ASIC architecture and design for high-performance AI processors; 15+ years silicon design; Verilog RTL; C/C++; SystemC; MS/PhD in EE/related field. Category: Engineering Seniority: Senior Level Tools: Verilog, SystemVerilog, RTL_verification, C++, Python, SystemC Commitment: Full Time Workplace: Hybrid Languages: English