About this role
SoC Interconnect Senior Architect at Openchip And Software Technologies SL. Location: Barcelona or Rome. Role: Collaborate teams, Define interconnects, Deliver RTL Requirements: 7+ years IP/SoC design; knowledge of SoC/NoC architectures; AMBA/AXI/CHI/ACE/APB; cache coherent memory; RISC-V familiarity; SystemVerilog/Verilog, C/C++, Python; RTL design and simulation; convergence cycles. Category: Engineering Seniority: Senior Level Tools: SystemVerilog, Verilog, C, C++, Python, simulation tools Commitment: Full Time Workplace: Hybrid Languages: English