About this role
Principal ASIC Design Verification Engineer at MaxLinear. Location: Bangalore, Karnataka, India. Role: lead verification, architect verification, mentor engineers Requirements: Lead verification architect; 12–16 years ASIC verif; AI-assisted verification; mentor teams; influence design-for-verification. Category: Engineering Seniority: Senior Level Tools: SystemVerilog, UVM, Verilog, C/C++, Linux/Unix, Python, Ethernet, PCIe, USB 3.0, SERDES, SystemC, DSP Commitment: Full Time Workplace: Onsite Languages: English