About this role
Lead Physical Design Engineer at Fractile. Location: London or Bristol. Role: drive implementation, synthesize timing, verify LVS Requirements: Senior/Principal level physical design engineer skilled in ASIC/SoC implementation, PPA optimization, and DFT/verification collaboration. Category: Engineering Seniority: Senior Level Tools: Cadence Innovus, Synopsys Fusion Compiler, Mentor Graphics Calibre, EDA scripting (TCL, Python, Perl) Commitment: Full Time Workplace: Onsite Languages: English