About this role
Project Design Lead (EX) at Nexperia. Location: San Jose, California, United States. Role: designing digital, verifying RTL, analyzing timing Requirements: Master’s in Electrical or Computer Engineering plus 2 years digital IC design; or Bachelor’s with 4 years; Cadence Xcelium, RTL/Verilog/SystemVerilog, FPGA prototyping, post-silicon validation, AI/ML in design. Category: Engineering Seniority: Senior Level Tools: Cadence Xcelium, Verilog, SystemVerilog, RTL design, FPGA prototyping Commitment: Full Time Workplace: Hybrid Languages: English