About this role
Verification Engineering Lead/Manager at Omnidesigntech. Location: Hyderabad or Bangalore. Role: Lead verification, Build team, Develop tests Requirements: Lead verification team; 8+ yrs EE, strong Verilog/SystemVerilog/UVM, testbench expertise. Category: Engineering Seniority: Senior Level Tools: Verilog, SystemVerilog, UVM, C/C++, Verdi, Siloti, Vera, Perl, Python Commitment: Full Time Workplace: Hybrid Languages: English