About this role
DFT Technical Lead at Marvell. Location: Petah-Tikva or Yokneam. Role: designing, verifying, leading Requirements: Bachelor’s in CS/EE; 12+ years ASIC VLSI design/verification; DFT design/verification (JTAG/iJTAG, SCAN, MBIST, BScan); SoC flows; EDA tools; lead DFT activities; strong analytical, debugging; RTL Verilog/SystemVerilog preferred. Category: Engineering Seniority: Senior Level Tools: Cadence, Synopsys, Siemens/Mentor Graphics, Verilog, SystemVerilog Commitment: Full Time Workplace: Onsite Languages: English