About this role
ASIC Chip Design Lead at Eridu AI Careers. Location: Saratoga, California, United States. Role: Develop RTL, Lead design, Collaborate PD Requirements: Hands-on RTL design, micro-architecture, full-chip integration, timing closure, and leadership across design, verification, and physical design. Category: Engineering Seniority: Senior Level Tools: Verilog, SystemVerilog, RTL, Timing Analysis, Synthesis, Physical Design Commitment: Full Time Workplace: Onsite Languages: English