About this role
Team Lead Digital Verification at Qualinx. Location: Delft or Delft. Role: verifying ASIC, develop testbenches, addressing timing Requirements: Bachelor’s degree in Electrical Engineering; 10+ years ASIC verification experience; 2+ years in team lead role; strong Verilog/EDA skills; experience with Cadence/Mentor; mixed-signal and RTL design experience; backend flow knowledge; strong programming (MATLAB, C/C++, Tcl). Category: Engineering Seniority: Senior Level Tools: SystemVerilog, UVM, Verilog, Cadence, Mentor Graphics, MATLAB, C, C++, Tcl Commitment: Full Time Workplace: Onsite Languages: English