About this role
Staff Digital Design Engineer – SOC Low Power, Clocking & Integration at Silabs. Location: Austin, Texas, United States. Role: developing architecture, integrating subsystems, debugging issues Requirements: BS/MS in Electrical Engineering, 10+ years digital CMOS IC design experience, expertise in Verilog/System Verilog, UPF/CPF, AXI/AHB/APB, RTL design, synthesis, timing, power analysis, simulation, scripting (Python/Perl/Tcl), and leading small teams. Category: Engineering Seniority: Senior Level Tools: Verilog, System Verilog, UPF, CPF, AXI, AHB, APB, RISC-V, C, Python, Perl, Tcl, Perforce, Git, Methodics Commitment: Full Time Workplace: Hybrid Languages: English